master clock meaning in English
母钟；时钟脉冲；主脉冲
母锺
直钟
主时钟
主钟
Examples
- Time service ; concepts and terms of master clocks
报时业务.母钟的概念和术语 - Master clock , microprocessor
微处理机主时钟 - Master clock frequency
主时钟频率 - Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains . the data transaction protocol comes from the most basic work way of uart . when the master clock is 16 . 7mhz , the pcm side and adpcm side clocks both are 2 . 38mhz , the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14 . 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14 . 7 us
在主时钟为16 . 7mhz ， pcm数据端与adpcm数据端时钟均为2 . 38mhz时，模拟结果表明从pcm的起始位输入uart接收器到adpcm终止位输出uart发送器的最大延迟为14 . 3 s ，从adpcm的起始位输入uart的接收器到pcm终止位输出uart发送器的最大延迟为14 . 7 s ，设计时尽可能的使编码与解码的时间相差不多，从结果看出基本达到这个要求。